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june 2016 docid027071 rev 4 1 / 14 this is information on a product in full production. www.st.com STD105N10F7AG automotive - grade n - channel 100 v, 6.8 m typ., 80 a, stripfet? f7 power mosfet in a dpak package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STD105N10F7AG 100 v 8 m 80 a 120 w ? designed for automotive applications and aec - q101 qualified ? among the lowest r ds(on) on the market ? excellent fom (figure of merit) ? low c rss /c iss ratio for emi immunity ? high avalanche ruggedness applications ? switching applications description this n - channel power mosfet utilizes stripfet? f7 technology with an enhanced trench gate structure that results in very low on - state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. table 1: device summary order code marking package packing STD105N10F7AG 105n10f7 dpak tape and reel am01475v1_ t ab d(2, t ab) g(1) s(3)
contents STD105N10F7AG 2 / 14 docid027071 rev 4 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 dpak (to - 252) type a2 package information ................................ . 10 5 revis ion history ................................ ................................ ............ 13
STD105N10F7AG electrical ratings docid027071 rev 4 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 100 v v gs gate - source voltage 20 v i d drain current (continuous) at t c = 25 c 80 a i d drain current (continuous) at t c = 100 c 62 a i dm (1) drain current (pulsed) 320 a p tot total dissipation at t c = 25 c 120 w t stg storage temperature range - 55 to 175 c t j operation junction temperature range notes: (1) pulse width limited by safe operating area. table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 1.25 c/w r thj - pcb (1) thermal resistance junction - pcb 50 notes: (1) when mounted on fr - 4 board of 1 inch2, 2oz cu. table 4: avalanche characteristics symbol parameter value unit e as single pulse avalanche energy t j = 25 c, l = 3.5 mh, i as = 15 a, v dd = 50 v, v gs = 10 v 400 mj
electrical characteristics STD105N10F7AG 4 / 14 docid027071 rev 4 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage (v gs = 0) i d = 250 a 100 v i dss zero gate voltage drain current (v gs = 0) v ds = 100 v 1 a v ds = 100 v, t c = 125 c (1) 100 a i gss gate body leakage current (v ds = 0) v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2.5 4.5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 40 a 6.8 8 m notes: (1) defined by design, not subject to production test. table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 50 v, f = 1 mhz, v gs = 0 v - 4369 - pf c oss output capacitance - 823 - pf c rss reverse transfer capacitance - 36 - pf q g total gate charge v dd = 50 v, i d = 80 a, v gs = 10 v (see figure 14: "test circuit for gate charge behavior" ) - 61 - nc q gs gate - source charge - 26 - nc q gd gate - drain charge - 13 - nc table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 50 v, i d = 40 a, r g = 4.7 , v gs = 10 v (see figure 13: "test circuit for resistive load switching times" and figure 18: "switching time waveform" ) - 27 - ns t r rise time - 40 - ns t d(off) turn - off delay time - 46 - ns t f fall time - 15 - ns
STD105N10F7AG electrical characteristics docid027071 rev 4 5 / 14 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 80 a i sdm (1) source - drain current (pulsed) - 320 a v sd (2) forward on voltage i sd = 80 a, v gs = 0 v - 1.2 v t rr reverse recovery time i sd = 80 a, di/dt = 100 a/s v dd = 80 v, t j = 150 c - 77 ns q rr reverse recovery charge - 146 nc i rrm reverse recovery current - 4 a notes: (1) pulse width limited by safe operating area. (2) pulsed: pulse duration = 300 s, duty cycle 1.5 %.
electrical characteristics STD105N10F7AG 6 / 14 docid027071 rev 4 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : normalized v (br)dss vs temperature figure 7 : static drain - source on - resistance
STD105N10F7AG electrical characteristics docid027071 rev 4 7 / 14 figure 8 : gate charge vs gate - source voltage figure 9 : capacitance variations figure 10 : normalized gate threshold voltage vs temperature figure 11 : normalized on - resistance vs temperature figure 12 : source - drain diode forward characteristics
test circuits STD105N10F7AG 8 / 14 docid027071 rev 4 3 test circuits figure 13 : test circuit fo r resistive load switching times figure 14 : test circuit for gate charge behavior figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unclamped inductive load test circuit figure 17 : unclamped inductive waveform figure 18 : switching time waveform
STD105N10F7AG package information docid027071 rev 4 9 / 14 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package infor mation STD105N10F7AG 10 / 14 docid027071 rev 4 4.1 dpak (to - 252) type a2 package information figure 19 : dpak (to - 252) type a2 package outline 0068772_type-a2_rev21
STD105N10F7AG package information docid027071 rev 4 11 / 14 table 9: dpak (to - 252) type a2 mechanical data dim. mm min. typ. max. a 2.20 2.40 a1 0.90 1.10 a2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 d 6.00 6.20 d1 4.95 5.10 5.25 e 6.40 6.60 e1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 h 9.35 10.10 l 1.00 1.50 l1 2.60 2.80 3.00 l2 0.65 0.80 0.95 l4 0.60 1.00 r 0.20 v2 0 8
package information STD105N10F7AG 12 / 14 docid027071 rev 4 figure 20 : dpak (to - 252) recommended footprint (dimensions are in mm)
STD105N10F7AG revision history docid027071 rev 4 13 / 14 5 revision history table 10: document revision history date revision changes 23 - oct - 2014 1 first release. 30 - oct - 2014 2 document status promoted from preliminary to production data. 20 - may - 2016 3 updated section 4.1: "dpak (to - 252) type a2 package information". minor text changes. 03 - jun - 2016 4 updated title and features in cover page. updated table 5: "o n/off states" . minor text changes.
STD105N10F7AG 14 / 14 docid027071 rev 4 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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